1. Field of the Invention
Methods and apparatuses consistent with the present invention relate to a complementary metal-oxide semiconductor (CMOS) amplifier, and more particularly, to an apparatus and method which can reduce a low frequency flicker noise in the CMOS amplifier.
2. Description of Related Art
With increasing developments in the field of a semiconductor technology, the size of devices which constitute a semiconductor circuit, such as a CMOS amplifier, is being reduced. As shown in FIG. 1, a CMOS amplifier 100 in the form of a differential amplifier which amplifies input differential signals V+ and V−, and outputs an amplified signal VOUT, is widely utilized in circuits of almost every field. Currently, a system for transmitting/receiving high speed wireless data, such as a mobile phone, a Digital Multimedia Broadcasting (DMB) phone, a Personal Digital Assistant (PDA), and an Ultra Wideband (UWB), is being developed. Configuration devices of the CMOS amplifier 100 for utilization in the system are also being miniaturized. While the communication system described above requires a high signal-to-noise (SNR) ratio, devices which constitute the CMOS amplifier 100 are being down-scaled and a low frequency flicker noise caused by this physical property, i.e. l/f noise, is annoying to users. To improve the low frequency noise as described above, a method of enlarging an active area of devices of the CMOS amplifier 100 may be utilized. However, in this case, since parasitic components increase, an operating frequency may be limited.
FIG. 2 illustrates a circuit 200 which is an example of a related art method for reducing the flicker noise of a CMOS amplifier 220. In this instance, the circuit 200 includes mixers 210 and 230 that respectively synthesize a signal RF1 or RF2 which have a certain frequency, in the front and the rear of the CMOS amplifier 220. However, even when utilizing the method as described above, at least one sixth-order low pass filter (LPF) 240 is required to remove a flicker noise such as a glitch from an input signal VIN. Accordingly, the size of the circuit is increased.
FIG. 3 illustrates a circuit 300 which depicts an example of another related art method for reducing the flicker noise of a CMOS amplifier 310. When a clock signal Ø1 is active, the circuit 300 enables an offset to be removed by turning on Metal-Oxide Semiconductor Field Effect Transistors (MOSFETs) M11, M12 and M13 and shorting both ends of a capacitor CAZ. After this, when a clock signal Ø2 is active, the circuit 300 enables the input signal VIN to be amplified in the CMOS amplifier 310 by turning on MOSFETs M21 and M22. As described above, a correlated double sampling (CDS) method samples and removes a l/f noise sampled in the case of activation of the clock signal Ø1. However, it is difficult to process a continuous input signal VIN due to the clock signals Ø1 and Ø2.